Navitas Semiconductor has launched its 5th-generation GeneSiC technology platform, a 1200 V SiC MOSFET line based on what the company calls Trench-Assisted Planar (TAP) architecture. The design combines the ruggedness of a planar gate structure with the performance benefits of a trench in the source region.
The headline improvement is a 35% better RDS(on) x QGD figure of merit compared to the previous-generation 1200 V technology, which translates to lower switching losses and the ability to operate at higher frequencies. The platform also achieves a roughly 25% improvement in the QGD/QGS ratio, which paired with a stable threshold voltage (VGS(th) ≥ 3 V) helps prevent parasitic turn-on in high-noise environments.
On the reliability side, Navitas is qualifying the parts to what it calls “AEC-Plus” grade—exceeding standard AEC-Q101 and JEDEC requirements. That includes 3x longer duration for static high-temperature, high-voltage stress testing and dynamic reverse bias and gate switching tests designed for fast-switching mission profiles. The company claims an extrapolated gate-oxide failure time exceeding one million years at 18 V operating VGS and 175° C.
“Our customers are redefining the boundaries of power conversion in AI data centers and energy infrastructure,” said Paul Wheeler, VP and GM of Navitas’ SiC business unit. “Significant technological improvements in our 5th-generation GeneSiC technology underscore Navitas’ commitment to delivering industry-leading performance and reliability in silicon carbide MOSFETs.”
The new platform complements Navitas’ existing ultra-high-voltage 2300 V and 3300 V SiC lines from the 4th-generation GeneSiC platform. New products based on the 5th-generation technology will be announced in the coming months. A white paper on the TAP architecture is available on the Navitas website.
Source: Navitas Semiconductor
